1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display (LCD) device, and more particularly, to a shift register for an LCD device. Embodiments of the present invention are suitable for a wide scope of applications. In particular, an embodiment of the present invention is suitabe for providing a shift register with a reduced number of switching devices for low manufacturing costs.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device displays an image by generating an electric field through a liquid crystal material to control light transmittance. The LCD device includes a liquid crystal panel with pixel areas in a matrix arrangement, and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, a plurality of gate lines and a plurality of data lines cross each other. Crossings of the gate lines and the data lines define pixel areas.
Pixel electrodes and a common electrode a formed on in the liquid crystal panel for applying the electric field to the respective pixel areas. Each of the pixel electrodes is connected to an associated one of the data lines via the source terminal and drain terminal of a switching device, such as a thin film transistor (TFT). The TFT is turned on in response to a scan pulse applied to the gate terminal thereof via an associated one of the gate lines, so as to supply a data signal on the associated data line to an associated one of the pixel electrodes.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for control of the gate driver and data driver, and a power supply for supplying various drive voltages to be used in the LCD device.
The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive liquid crystal cells in the liquid crystal panel line-by-line. The gate driver includes a shift register for sequentially outputting the scan pulses. The data driver supplies pixel voltage signals respectively to ones of the data lines associated with a given one of the gate lines whenever a corresponding one of the scan pulses is supplied to the given gate line. Hence, the LCD device displays an image by adjusting light transmittance with an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal on a cell-by-cell basis.
The shift register has a plurality of stages arranged in a line. Each of the stages is connected to a corresponding one of the gate lines to supply a corresponding one of the scan pulses to the corresponding gate line. Each of the stages is enabled in response to the scan pulse from the previous stage and disabled in response to the scan pulse from the next stage.
In general, each stage includes a node controller for controlling a charging/discharging operation of an enabling node and disabling node, a pull-up switching device for outputting the scan pulse according to the state of the enabling node, and a pull-down switching device for outputting an OFF voltage according to the state of the disabling node.
Each stage outputs the OFF voltage for an entire frame period, except for one horizontal period (1H) during the frame period. Accordingly, the disabling node is held in its charged state much longer than the enabling node is held in its charged state. Hence, the pull-down switching device connected to the disabling node is kept turned on much longer than the pull-up switching device causing deterioratuion of the pull-down switching device.
A a shift register having a stage with two or more disabling nodes has been developed to solve this problem. In this shift register, the disabling nodes are alternately charged on a frame-by-frame basis. Such an arrangement prevents deterioration of the pull-down switching device connected to each of the disabling nodes.
FIG. 1 is a schematic description of a stage of a shift register in accordance with the related art. Referring to FIG. 1, the related art stage includes a node controller 105 for controlling a charging/discharging operation of an enabling node Q, the charging/discharging operation of a first disabling node QB1 and the charging/discharging operation of a second disabling node QB2, a pull-up switching device Tru for outputting a scan pulse Vout according to the state of the enabling node Q, a first pull-down switching device Trd1 for outputting an OFF voltage Vdc2 according to the state of the first disabling node QB1, and a second pull-down switching device Trd2 for outputting the OFF voltage Vdc2 according to the state of the second disabling node QB2.
When the stage is disabled, one of the first and second disabling nodes QB1 and QB2 is charged and the other is discharged. For example, when the first disabling node QB1 is charged and the second disabling node QB2 is discharged, the first pull-down switching device Trd1 with its gate terminal connected to the first disabling node QB1 is operated and the second pull-down switching device Trd2 with its gate terminal connected to the second disabling node QB2 is not operated. The second pull-down switching device Trd2 remains idle. Thus, deterioration of the pull-down switching devices Trd1 and Trd2 is prevented by alternately driving the first pull-down switching device Trd1 and the second pull-down switching device Trd2.
However, this structure increases the number of switching devices in the node controller 105 of the related art stage. The node controller 105 must have a large number of switching devices to control one enabling node Q and two disabling nodes QB1 and QB2. The use of a large number of switching devices increases the size of the stage and the manufacturing cost.